The present invention relates to semiconductor devices and, more particularly, to a method of mounting a protective cover on a semiconductor wafer substrate on which one or more devices have been fabricated.
It is possible to implement many types of devices on a semiconductor wafer using known processes. Typically, multiple devices are implemented on a single semiconductor wafer and then are separated into individual components by sawing the wafer into multiple parts (xe2x80x9cdicingxe2x80x9d), each part containing one or more devices. To avoid excessive heat build-up on the wafer and to prevent the devices from being damaged by heating which may occur during dicing, it is conventional to spray the wafer with water or another type of liquid to cool the wafer during the dicing process.
For many types of devices, using liquid to cool the wafer during the dicing process does not affect the function of the device after dicing has been completed. However, other semiconductor devices are extremely fragile and/or sensitive to, and may be negatively affected by, environmental hazards, such as dust or other particulates, moisture, and inadvertent scratching, collectively xe2x80x9ccontaminants.xe2x80x9d
One example of a device that may be adversely affected by being exposed to contaminants during the dicing process is a micro-mechanical structure, useful, e.g., as an acceleration or pressure sensor. A typical micro-mechanical structure has a cantilevered beam or other structure that resides above the surface of the substrate. Movement of the beam of the micro-mechanical structure relative to the base may be used to determine a physical variable, such as acceleration or pressure. Particulate matter or moisture may impede movement of the micro-mechanical structure or may otherwise adversely affect generation of a signal from movement of the micro-mechanical structure.
As a result, it has become common in the industry to protect micro-mechanical structures and other devices resident on a semiconductor substrate after fabrication to prevent active areas of the semiconductor substrate from becoming contaminated during subsequent processing. As used herein, the term xe2x80x9cactive areaxe2x80x9d will be used to refer to that portion of a semiconductor substrate that should be or is desired to be protected from contamination. An xe2x80x9cactive areaxe2x80x9d as that term is used herein may, but need not, include a micro-mechanical structure. Multiple active areas may be formed on a single wafer.
There are several known techniques that may be used to protect the active area of a semiconductor substrate during processing. One method involves placing several layers of protective tape over the active areas to prevent the active areas from being contaminated. In this method, a first layer of tape having holes corresponding to the locations of the active areas is initially applied to the wafer and then a second layer of tape is applied over an exposed surface of the first layer of tape. This method requires the wafer to be diced from the back side of the wafer instead of the front side of the wafer, which makes it more difficult to align the dicing saw so that the dicing saw does not cut through the active areas on the wafer. An exemplary saw usable in this context is disclosed in U.S. Pat. No. 5,356,681, the content of which is hereby incorporated by reference. Moreover, the tape requires substantial surface area to be effective, thus reducing the density of active areas on the semiconductor. As used herein, the term density will be used to refer to the number of active areas per unit area that may be formed on any one wafer.
A second known technique of protecting active areas of the silicon wafer is to apply a protective cap wafer to an exposed surface of the semiconductor substrate containing the active areas prior to dicing. Typically, the protective cap wafer is sealed to the semiconductor substrate with a lead oxide glass frit or another sealant. This sealant is screen printed on the cap and then bonded to the semiconductor substrate under heat and pressure to form individual hermetic seals around an active area on the semiconductor substrate. The micro-mechanical structures or other devices in the active areas are sealed below the cap wafer and are free to move, yet are protected from the external environmental hazards. This technique is advantageous in that it allows standard front side dicing to be used to separate the semiconductor wafer into individual elements. Screen printing lead oxide glass frit also uses less surface area than the tape method, thus increasing density.
Unfortunately, constraints associated with screen printing limit the accuracy with which the sealant may be deposited on the cap and the minimum width of the lines that may be formed. Thus, although screen printing sealant is better than using the tape method, limitations attendant to screen printing require the sealant to occupy an overly large area on the semiconductor wafer, thus limiting the overall yield achievable with this method.
For example, as shown in FIG. 1, screen printing sealant results in a relatively thick line 100 of sealant. Specifically, using current technology, the minimum line width achievable using screen printing is about 150 xcexcm. Moreover, screen printing does not permit interior comers 105 to be accurately defined, thus necessitating an offset between an interior edge of the line of sealant and the outer edge of the active area, shown in dashed lines in FIG. 10. Finally the width of the sealant is limited by inherent inaccuracies in the screen printing process. For example, if a line of sealant with a width of 150 xcexcm is printed, the variation in line width may be up to approximately 25 xcexcm.
Photolithography has been attempted, unsuccessfully, as a method to reduce the width of lines of sealant. For example, one attempt at using photolithography is set forth in FIGS. 2a-2e. In this method, a sealant 30 is first screen printed on the silicon cap wafer 28 incurred. Subsequently, as shown in FIG. 2b, a photoresist 32 is then applied over the sealant 30 and patterned, as shown in FIG. 2c, to define regions where it would be desirable to have sealant 30 remain on the silicon cap wafer 28 after subsequent processing. The sealant 30 then is etched, as shown in FIG. 2d, to remove excess sealant 30 from the areas other than where desired for sealing the silicon cap wafer 28 to a semiconductor wafer including active devices. After the excess sealant 30 has been removed, the remaining photoresist 32 is removed to produce a silicon cap wafer 28 carrying areas of sealant 30 defined by photolithography, as shown in FIG. 2e. 
This method has proven satisfactory for depositing lines of solder sealant and other sealants for which acceptable etchants have been developed. Unfortunately, however, solder is unsuitable for many applications because of a mismatch between the coefficient of thermal expansion between typical solders and semiconductor substrates, which can cause the wafer to warp or crack. It is thus necessary to use a material, such as lead oxide glass, with a coefficient of thermal expansion that more closely matches the coefficient of thermal expansion of the substrates. Since lead oxide glass is a two-phase mixture, however, applicants have found that known etchants will attack preferentially only one phase of the two-phase mixture forming the lead-oxide glass resulting in a rather jagged line of sealant. Accordingly, it is not generally possible to etch two phase sealants such as lead-oxide glass.
Another attempt to optically define lines of sealant is illustrated in FIGS. 3a-3b. According to this embodiment, a photoresist and sealant mixture 38 is first coated on the silicon cap wafer 28 (FIG. 3a) and then patterned (FIG. 3b) to define regions where the sealant will remain after firing. The sealant and photoresist mixture 38 is hardened by firing or baking to remove excess solvent. One potential sealant/photoresist mixture 38 for use in this process is available from Dupont(copyright) under the trademark FODEL(copyright). FODEL(copyright) is a material that incorporates photosensitive polymers and glass frit sealant materials, to allow patterning using UV light exposure. Unfortunately, FODEL(copyright) has a relatively high glazing temperature, and is thus not usable with many active areas, since heating the active area sufficiently to cause the FODEL(copyright) to reflow will damage the semiconductor device.
Thus, there is currently no method available to form narrow lines of sealant useable for sealing a cap wafer to an active area. Accordingly, what is needed is a method for capping active areas of a semiconductor wafer, while providing a high density of active areas on the semiconductor wafer.
In view of the foregoing, it would be advantageous to have a method for capping active areas of a semiconductor wafer, while providing a high density of active areas on the semiconductor wafer.
According to one embodiment of this invention, a method of defining sealant regions on a semiconductor wafer includes the steps of applying a photoimageable layer, photoimaging the photoimageable layer to define a pattern including remaining regions of the photoimageable layer and removed regions of the photoimageable layer, using the removed regions of the photoimageable layer to define the sealant regions on the semiconductor wafer; and applying sealant to the sealant regions defined by the pattern.
The method may further include one or more steps, such as curing the sealant to harden the sealant, removing the remaining regions after applying the sealant to the sealant regions, removing excess sealant not within the sealant regions, and using the sealant material to form at least one seal, such as a hermetic seal around at least one active area formed on the semiconductor wafer or a second semiconductor wafer.
According to another embodiment of this invention, a method of defining sealant regions on a semiconductor wafer using photolithography includes the steps of applying a photoresist to the semiconductor wafer, patterning the photoresist on the semiconductor wafer to define a pattern of photoresist including remaining regions of photoresist and removed regions of photoresist, applying sealant to the pattern, removing excess sealant, and removing the remaining photoresist.
In this embodiment, the steps of removing the excess sealant and removing the remaining photoresist may be performed in a lift-off process by etching the underlying photoresist. The step of applying sealant to the pattern may be accomplished by screen printing sealant onto the semiconductor wafer using a blank mask or a patterned mask, or by using a squeegee to distribute sealant into the pattern in the photoresist. The method may include the step of curing the photoresist prior to applying the sealant.
The method may also include the steps of curing the sealant and removing the excess sealant after curing the sealant, for example, by polishing. The method may further include the step of using the sealant material to form at least one seal, such as a hermetic seal, around at least one active area formed on the semiconductor wafer or a second semiconductor wafer. In this method, the sealant may be lead oxide glass and the photoresist may be polyamide.
According to a further embodiment of this invention, a method of defining sealant regions on a semiconductor wafer using photolithography includes the steps of providing a semiconductor wafer, applying a first layer of photoresist to the semiconductor wafer, patterning the first layer of photoresist to define a first pattern of photoresist including first remaining regions of photoresist and first removed regions of photoresist, etching the semiconductor wafer to form a topography on the semiconductor wafer, removing the first remaining regions of photoresist, and applying a layer of sealant to the topography of the semiconductor wafer.
In this method, the step of applying the layer of sealant may include the steps of applying a second layer of photoresist to the semiconductor wafer, patterning the second layer of photoresist to define a second pattern of photoresist including second remaining regions of photoresist and second removed regions of photoresist, applying sealant to the patterned second layer of photoresist, and removing excess sealant. In this method, a mask used to pattern the second layer of photoresist may be the inversed mask used to pattern the first layer of photoresist. Optionally, in this method, the step of etching the semiconductor wafer may occur prior to the step of applying sealant.